VLSI & Chip Design Final Year Projects
RTL design and verification projects in Verilog/VHDL for ASIC and FPGA implementation.
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8-Bit RISC Processor on FPGA
A pipelined 8-bit RISC CPU core implemented and validated on a Xilinx FPGA dev board.
10-12 weeks
Beginner Friendly
UART Communication Protocol Design
A fully synthesizable UART transmitter-receiver core verified with a custom testbench.
6-8 weeks
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Low-Power ALU Design Using Verilog
A clock-gated arithmetic logic unit optimized for low power consumption, synthesized on FPGA.
8-10 weeks
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Memory Controller Design & Verification
An SDRAM memory controller with a UVM-based verification environment for functional coverage.
8-10 weeks
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